`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    07:47:38 04/20/2011 
// Design Name: 
// Module Name:    Controller 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Controller(instrControl, RegWrite, MemtoReg, branch, MemRead, MemWrite, ALUSrc1, ALUSrc2, ALUOp, 
							doJmp, liRlw, ID_Flush, RorNot);
    

	input [3:0] instrControl;
	output doJmp;
//	output doBra;
	output RegWrite;
	output MemtoReg;
	output branch;
	output MemRead;
	output MemWrite;
//	output RegDst;
	output ALUSrc1; //Rs vs 0
	output ALUSrc2; //Rt vs immediate
	output [3:0] ALUOp;
//	output wbMuxSel;
	output RorNot;
	output ID_Flush;
	output [1:0] liRlw;
	
	reg doJmp;
//	reg doBra;
	reg [3:0] jumpPC;
	reg [11:0] jumpInstr;
	reg RegWrite;
	reg MemtoReg;
	reg branch;
	reg MemRead;
	reg MemWrite;
//	reg RegDst;
	reg ALUSrc1;
	reg ALUSrc2;
	reg [3:0] ALUOp;
//	reg wbMuxSel;
	reg RorNot;
	reg ID_Flush;
	reg [1:0] liRlw;
	
	//control signals block
	always @ (instrControl)
	begin
		casex (instrControl)
			4'b0001: begin //add
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b1000;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b0010: begin //sub
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0001;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b0011: begin //and
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0010;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b0100: begin //or
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0011;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b0101: begin //nor
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0100;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b0110: begin //shift left
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0101;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b0111: begin //shift right
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0110;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b1000: begin //set less than
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0111;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b1001: begin //set greater than
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0000;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b01;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
			4'b1010: begin //load immediate
						RegWrite <= 1'b1;
						MemtoReg <= 1'b1;
						branch <= 1'b0;
						MemRead <= 1'b1;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b0;
						ALUSrc1 <= 1'b1;
						ALUSrc2 <= 1'b1;
						ALUOp <= 4'b1000;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b00;
						ID_Flush <= 1'b1;
				//		wbMuxSel <= 1'b0;
						RorNot <= 1'b0;
						end
			4'b1011: begin //load word
						RegWrite <= 1'b1;
						MemtoReg <= 1'b1;
						branch <= 1'b0;
						MemRead <= 1'b1;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b0;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b1;
						ALUOp <= 4'b1000;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b10;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b0;
						end
			4'b1100: begin //save word
						RegWrite <= 1'b0;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b1;
				//		RegDst <= 1'b0;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b1;
						ALUOp <= 4'b1000;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b10;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b0;
						RorNot <= 1'b0;
						end
			4'b1101: begin //branch if equal b
						RegWrite <= 1'b0;
						MemtoReg <= 1'b0;
						branch <= 1'b1;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b1;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b0001;
						doJmp <= 1'b0;
				//		doBra <= 1'b1;
						liRlw <= 2'b00;
						ID_Flush <= 1'b0;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b0;
						end
			4'b1110: begin //jump
						RegWrite <= 1'b0;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b0;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b1000;
						doJmp <= 1'b1;
				//		doBra <= 1'b0;
						liRlw <= 2'b00;
						ID_Flush <= 1'b1;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b0;
						end
			4'b1111: begin //jump and link
						RegWrite <= 1'b1;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b0;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b1000;
						doJmp <= 1'b1;
				//		doBra <= 1'b0;
						liRlw <= 2'b00;
						ID_Flush <= 1'b1;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b0;
						end
			default: begin
						RegWrite <= 1'b0;
						MemtoReg <= 1'b0;
						branch <= 1'b0;
						MemRead <= 1'b0;
						MemWrite <= 1'b0;
				//		RegDst <= 1'b0;
						ALUSrc1 <= 1'b0;
						ALUSrc2 <= 1'b0;
						ALUOp <= 4'b1000;
						doJmp <= 1'b0;
				//		doBra <= 1'b0;
						liRlw <= 2'b00;
						ID_Flush <= 1'b1;
				//		wbMuxSel <= 1'b1;
						RorNot <= 1'b1;
						end
		endcase
	end
	
endmodule
